The invention relates to circuitry for providing clock pulses from raw input data which does not include regular clock pulses and which may be, for example, a signal of modified frequency modulation (MFM). Such modulation includes only clock pulses between two consecutive zeros of the raw data signal and the data pulses of the raw data signal may be shifted with respect to their proper and normal times of occurrence due to transmission difficulties.
It has previously been proposed to provide clock pulses for a modified frequency modulation raw data signal utilizing an oscillator which is controlled by an increase frequency signal and a decrease frequency signal causing the oscillator to respectively increase and decrease in frequency of oscillation. The increase frequency signal and the decrease frequency signal rise alternately so that the frequency of oscillation of the oscillator is first increased and then decreased, and the length of one of these signals is varied in accordance with a measure of the phase error between the output of the oscillator and the data pulses of the raw data signal. The length of time between consecutive rises of one of these signals is the normal length of time (without time shifting) between two consecutive data pulses of the raw data signal, so that if the pulses of these two signals are equal in length each of these pulses occupy one-half of the time between two consecutive data pulses (without time shifting) of the raw data signal. In the event that a pulse of one of these increase and decrease frequency signals is longer than a corresponding pulse of the other of these two signals, there is an overlap of the pulses of these two signals. Since the pulses of the increase and decrease signals are nominally up for one-half of the time between two consecutive data pulses in the raw data signal, the change in frequency of the oscillator during correction (even when there should have been no correction) is unduly great. Also, with this arrangement, if there is the overlap just mentioned (which would be produced by the case in which a data pulse is early), an error is introduced in the oscillating frequency of the oscillator since both the increase and decrease frequency signals are in control at the same time. Two current sources must be used for controlling the oscillator due to this overlap that occurs with an early data pulse, and the current sources must therefore be accurately matched. Circuitry of this type is described in general in the Technical Disclosure Bulletin of IBM Corporation, December, 1971, page 2171.